Fractional-N phase-locked loop (PLL) circuits are used in many clocking applications due to flexibility in frequency planning. A digital sigma delta modulator (SDM) is one of the main building blocks in a fractional-N PLL. The SDM circuit provides the PLL with the flexibility of having a fractional multiplication factor with the benefit of noise shaping by dithering the divide value of the PLL's feedback dividers. The noise shaping ability of the SDM helps limit the jitter contribution of fractional operation in a fractional-N PLL. Practical SDM architectures, however, suffer from having a limited stable input range. For example, a multi-stage noise shaping (MASH) architecture, which is commonly used in SDMs, has an input range from zero to one. This small input range limits the fractional-N PLL's use in applications such as tracking part-per million (PPM) and spread spectrum clocking (SSC). The limited input range of the SDM prevents its output fractional word from dynamically crossing an integer boundary without causing large jitter in the PLL. Accordingly, it is desirable to provide an SDM circuit having a wider input range.